Travaux de recherche
Mes sujets de recherche incluent les transistors à effet de champ (MOSFET) et les mémoires à changement de phase (PCM). Les procédés de fabrication, la caracterisation physique, la simulation TCAD, la modélisation électrique, la conception de circuits intégrés analogiques et numériques, la caracterisation électrique, sont des sujets sur lesquels je travaille.
Profil Google Scholar : https://scholar.google.com/citations?user=cgETodsAAAAJ&hl=en&oi=sra
Profil IEEE : https://ieeexplore.ieee.org/author/37088934253
Profil Elsevier (Scopus) : https://www.scopus.com/authid/detail.uri?authorId=57368154600
Profil ORCID : https://orcid.org/0000-0001-5483-6557
Profil ResearchGate : https://www.researchgate.net/profile/Paul_Devoge
Profil HAL : https://hal.archives-ouvertes.fr/search/index/q/*/authIdHal_s/paul-devoge
P. Devoge et al., "Device and circuit-level evaluation of a zero-cost transistor architecture developed via process optimization," Solid-State Electronics, ISSN 0038-1101, vold. 201, pp. 108575, 2023, doi: 10.1016/j.sse.2022.108575.
P. Devoge et al., "A Schmitt trigger to benchmark the performance of a new zero-cost transistor," 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-4, 2022, doi: 10.1109/ICECS202256217.2022.9970962.
P. Devoge et al., "Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation," 2022 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, pp. 1-5, 2022, doi: 10.1109/IIRW56459.2022.10032763.
P. Devoge et al., "Hot-carrier reliability and performance study of transistors with variable gate-to-drain/source overlap," Microelectronics Reliability, special issue for ESREF 2022 : 33rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ISSN 0026-2714, vol. 138, pp. 114699, 2022, doi: 10.1016/j.microrel.2022.114699.
P. Devoge et al., "Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 761-764, 2022,doi: 10.1109/ISCAS48785.2022.9937483.
R. Simola, P. Devoge, P. Boivin, S. Niel, R. Gonella, A. Redaelli, "Thermal disturb TCAD simulation of phase-change memory device," 2022 28th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), pp. 1-4, 2022, doi: 10.1109/THERMINIC57263.2022.9950683.
P. Devoge et al., "Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology," Microelectronics Reliability, special issue for ESREF 2021 : 32th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ISSN 0026-2714, vol. 126, pp. 114265, 2021, doi: 10.1016/j.microrel.2021.114265.
P. Devoge et al., "Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology," 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1-5, 2021, doi: 10.1109/DTIS53253.2021.9505137.
R. Simola, P. Devoge, P. Boivin, A. Regnier, F. Arnaud, R. Gonella, "TCAD Investigation of Thermal Disturb During RESET Operation in 28nm ePCM Technology Node," E\PCOS 2019 - European Phase-Change and Ovonic Symposium, 2019, poster.